`timescale 1ns/10ps

module dummy_dut;
initial begin
  $display("Dummy dut,pelase replace to real dut");
end
endmodule

module  bench_top;

reg raw_clk;
reg clk_enable;
reg rstn;
reg sim_enable;

wire clk=raw_clk&clk_enable;

initial
begin
  raw_clk   = 0;
  clk_enable = 0;
  rstn = 0;
  sim_enable = 0;
  @(posedge sim_enable);
  #1000
  rstn = 1;
#10000
  $finish;
end

initial
begin
#10ms
  $display("=======================");
  $display("Timeout: 10ms expired");
  $display("=======================");
  $finish;
end

always #5  raw_clk = ~raw_clk;

always @(negedge raw_clk) begin
  if(sim_enable) begin
    clk_enable=1;
  end
end

dummy_dut u0_dut();

endmodule
